(A) Field of the Invention
The present invention relates to a memory storage device and method for operating the same. More specifically, the present invention relates to a non-volatile memory storage device and method for operating the same.
(B) Description of Related Art
FIG. 1 illustrates an 8-bit flash memory storage device 10 including a flash controller 11 and a flash memory 12. The flash controller 11 has a flash control circuit 13 which can issue a chip-enable (CE) signal to access the flash memory 12. An 8-bit flash data bus FD[7:0] is connected between the flash control circuit 13 and the flash memory 12.
FIG. 2 illustrates a 16-bit flash memory storage device 20 including a flash controller 21 and a flash memory 22. The flash memory 22 has two flash memory chips 221 and 222. The flash controller 21 has a flash control circuit 23 that can issue a CE signal to access the flash memory chips 221 and 222. A 16-bit flash data bus FD[15:0] is connected between the flash control circuit 23 and the flash memory chips 221 and 222.
FIG. 3 illustrates a flash memory storage device 30, which is popularly used in current flash memory storage devices or memory card devices, including a flash controller 31 and a flash memory 32. The flash memory 32 has a plurality of flash memory chips 34. The flash controller 31 has a flash control circuit 33 that can issue a plurality of CE signals (CE[0] to CE[15]) to access the flash memory chips 34 of the flash memory 32. A 16-bit flash data bus FD[15:0] is connected between the flash control circuit 33 and the flash memory chips 34.
In order to increase the performance of memory storage devices, it is common to increase the number of data buses, resulting in a need for more flash control circuits. As shown in FIG. 4, a flash controller 41 of a flash memory storage device 40 needs 64-bit data bus in total. Four control circuits, i.e., Flash Control Circuit 0, Flash Control Circuit 1, Flash Control Circuit 2 and Flash Control Circuit 3, are used, and each controls a 16-bit data bus. Flash Control Circuit 0 generates CE[15:0] to control the flash memory chips 42 at the first two rows, and FD[15:0] is the data bus between the Flash Control Circuit 0 and the flash memory chips 42. Likewise, Flash Control Circuit 1 generates CE[31:16] to control the flash memory chips 42 at the third and fourth rows, and FD[31:16] is the data bus thereof. Flash Control Circuit 2 generates CE[47:32] to control the flash memory chips 42 at the fifth and sixth rows, and FD[47:32] is the data bus thereof. Flash Control Circuit 3 generates CE[63:48] to control the flash memory chips 42 at the seventh and eighth rows, and FD[63:48] is the data bus thereof. Accordingly, 64 CE pads are needed for the flash controller 41. However, more CE chip pads would increase the package size and cost.
FIG. 5 illustrates a timing diagram for the flash memory storage device 40 in FIG. 4. “U” indicates CE update timing, and the CE signals CE[0], CE[16], CE[32] and CE[48], corresponding to the timings “U” for Flash Control Circuit 0, Flash Control Circuit 1, Flash Control Circuit 2 and Flash Control Circuit 3, are changed from “1” to “0” to access the first column of flash memory chips 42, respectively. Then, CE[0], CE[16], CE[32], and CE[48] are changed from “0” to “1” after accessing the first column of flash memory chips 42, respectively.
FIG. 6 illustrates a timing diagram of the flash memory storage device 40 in which the operation of every two neighboring columns of flash memory chips are interleaved (so-called interleave-2), i.e., they do not operate at the same time. CE[0] and CE[1], CE[16] and CE[17], CE[32] and CE[33], CE[48] and CE[49] are interleaved, i.e., CE[0] and CE[1] will not be “0” at the same time, CE[16] and CE[17] will not be “0” at the same time, CE[32] and CE[33] will not be “0” at the same time, and CE[48] and CE[49] will not be “0” at the same time. But, CE signals of each flash control circuit work independently, e.g., CE[0] and CE[1] do not care CE[16], CE[17], CE[32], CE[33], CE[48], and CE[49]. In another embodiment, the operation of every four neighboring columns of flash memory chips are interleaved (so-called interleave-4). For instance, CE[0], CE[1], CE[2], and CE[3] are interleaved.
The increase of performance for the flash memory storage devices may incur more power consumption. Peak power demand will grow dramatically when the flash control circuits execute flash commands at the same time. For instance, for the 8-bit memory storage device 10 shown in FIG. 1, the peak current is approximately 125 mA to 133 mA. For the 16-bit memory storage device 20 shown in FIG. 2, the peak current is approximately 230 mA to 239 mA. The memory storage devices 10 and 20 each have only one control circuit, and it can be seen that the peak current will increase tremendously as the number of control circuits increases. As shown in FIG. 7, when the Flash Control Circuit 0, Flash Control Circuit 1, Flash Control Circuit 2 and Flash Control Circuit 3 execute flash commands “60” and “D0” at the same time, a very high peak power consumption occurs at the end of “D0”. There is therefore a challenge to reduce the power consumption of the memory device with high performance.